Maskless middle-of-line liner deposition

US7049193B2 · kind B2 · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Michael Maldei · Durham, US
• Jinhwan Lee · Raleigh, US
• Guenter Gerstmeier · Chapel Hill, US
• Brian Cousineau · Burlington, US
• Jon Berry · Durham, US
• Steven Baker · Apex, US
• Malati Hedge · Cary, US

Key dates

• Filing date: Oct 7, 2004
• Grant date: May 23, 2006
• Expiry date: Nov 10, 2024

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B12/488
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A process for fabricating a semiconductor structure, wherein the semiconductor structure includes a core region and a periphery region. The core region includes a plurality of transistors and the periphery region includes a plurality of transistors. The process includes depositing a middle-of-line liner using plasma enhanced chemical vapor deposition overlying the semiconductor structure. By using a plasma enhanced chemical vapor deposition the amount of MOL liner deposited in the core region and the periphery region can be controlled depending on the distances between transistors in the core region and periphery region.