Semiconductor memory cell with trench capacitor and selection transistor and method for fabricating it

US7049647B2 · kind B2 · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Wolfram Karcher · Osterburken, DE
• Dietmar Temmler · Dresden, DE
• Martin Schrems · Langenbruck, DE

Key dates

• Filing date: Mar 17, 2003
• Grant date: May 23, 2006
• Expiry date: Mar 22, 2023

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B12/373

Abstract

A semiconductor memory cell is formed in a substrate and includes a trench capacitor and a selection transistor. The trench capacitor includes a capacitor dielectric and a conductive trench filling. Disposed on the conductive trench filling is a diffusion barrier on which an epitaxial layer is formed. The selection transistor is disposed as a planar transistor above the trench capacitor. A drain doping region of the selection transistor is disposed in the epitaxial layer.