Asymmetric comparator for low power applications
US7049857B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jan 17, 2002 |
| Grant date | May 23, 2006 |
| Priority date | — |
| Expiry date | Oct 12, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/082
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method and structure for comparing an input signal to a reference signal using a comparator comprises a circuit for setting a trip point of a rising edge of an input signal according to a value of an external voltage reference; and at least two transistors, in the circuit, for setting a trip point of a falling edge of an input signal, according to a width-to-length ratio of the at least two transistors. Moreover, the at least two transistors comprises a first transistor of length (Lx) and a width of (Wx); and a second transistor of length (Ly) and a width of (Wy), wherein the width-to-length ratio equals (WxLy)/(WyLx). The trip point of a falling edge of an input signal increases (decreases) by increasing (decreasing) the width-to-length ratio.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.