Nonvolatile semiconductor memory device having reduced erasing time
US7050336B2 · kind B2 · utility
7Cited by
11References
13Claims
0Family size
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Key dates
| Filing date | Sep 1, 2004 |
| Grant date | May 23, 2006 |
| Priority date | — |
| Expiry date | Oct 10, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/16
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An operation of erasing data in a memory block of a nonvolatile semiconductor memory device employs an operation of collectively applying an erase pulse to the memory block, and an operation of collectively applying an erase pulse to a limited region in the memory block. Thereby, the number of the erase pulses excessively applied to the memory cells, which passed verify, can be reduced as compared with a conventional structure so that the number of the memory cells to be subjected to over-erase recovery write decreases, and the total block erase time can be short.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.