Built-in testing methodology in flash memory
US7050343B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 27, 2004 |
| Grant date | May 23, 2006 |
| Priority date | — |
| Expiry date | Apr 18, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/0405
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An Electric Wafer Sort (EWS) flow is implemented by expanding the functions of the micro-controller embedded in a FLASH EPROM memory device and of the integrated test structures. Test routines are executed by the onboard micro-controllers (that may be reading either from an embedded ROM or from a GLOBAL CACHE provided) internally without involving any external complex or expensive test equipment to control the test program. The device architecture is transparent from a tester point of view, with a standard interface having a set of defined commands and instructions to be interpreted by the on board microcontroller and internally executed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.