Scalable on chip network
US7051150B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 29, 2002 |
| Grant date | May 23, 2006 |
| Priority date | — |
| Expiry date | Oct 15, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/78
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A scalable network for supporting an application using processing elements including ports, an interconnect, port interfaces, and an arbiter. Each port conforms to a consistent port interface protocol regardless of number of ports, frequency of operation, maximum datum width or data path concurrency. The interconnect has a scalable maximum datum width and a scalable data path concurrency, and includes selectable data paths between any two ports to enable transfer of datums between the ports. Each port interface formulates packets for transmission and receives packets via the corresponding port and the interconnect, where each packet includes one or more datums. The arbiter controls packet transfer via the interconnect between source and destination ports. The interconnect has a scalable data path concurrency. Pipeline stages may be added to support a selected clock frequency. The OCN may be a component library including bus gasket, interconnect and arbiter components.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.