Pseudo fail bit map generation for RAMS during component test and burn-in in a manufacturing environment
US7051253B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 16, 2001 |
| Grant date | May 23, 2006 |
| Priority date | — |
| Expiry date | May 31, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
According to an embodiment of the present invention, a method is provided for determining a fail string for a device. The method includes determining a test pattern for a portion of an address space wherein the test pattern includes at least one address in the address space and the portion of the address space includes at least one x address and at least one y addresses. The method executes a test a plurality of times for each test pattern, wherein every combination of the test pattern is tested, wherein the combinations include each address held at a first potential for at least a first test and a second potential for at least a second test. The method includes determining a fail string for the device including pass/fail results for the test pattern, and combining the pass/fail results in the fail string.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.