Deep N wells in triple well structures and method for fabricating same
US7052966B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 9, 2003 |
| Grant date | May 30, 2006 |
| Priority date | — |
| Expiry date | May 15, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/859
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A disclosed method for fabricating a structure in a semiconductor die comprises steps of implanting a deep N well in a substrate, depositing an epitaxial layer over the substrate, and forming a P well and a lateral isolation N well over the deep N well, wherein the lateral isolation N well and the P well are fabricated in the substrate and the epitaxial layer, and wherein the lateral isolation N well laterally surrounds the P well, and wherein the deep N well and the lateral isolation N well electrically isolate the P well. Implanting a deep N well can comprise steps of depositing a screen oxide layer over the substrate, forming a mask over the screen oxide layer, implanting the deep N well in the substrate, removing the mask, and removing the screen oxide layer. Depositing the epitaxial layer can comprise depositing a single crystal silicon over the substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.