Semiconductor device based on Si-Ge with high stress liner for enhanced channel carrier mobility
US7053400B2 · kind B2 · utility
36Cited by
4References
9Claims
0Family size
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Key dates
| Filing date | May 5, 2004 |
| Grant date | May 30, 2006 |
| Priority date | — |
| Expiry date | May 15, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/0212
Abstract
The carrier mobility in transistor channel regions of Si—Ge devices is increased by employing a stressed liner. Embodiments include applying a high compressive or tensile stressed film overlying relaxed source/drain regions. Other embodiments include applying a high compressively or high tensilely stressed film, after post silicide spacer removal, over gate electrodes and strained Si source/drain regions of P-channel or N-channel transistors, respectively.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.