Successive approximation analog/digital converter with reduced chip area
US7053810B2 · kind B2 · utility
3Cited by
6References
4Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 14, 2005 |
| Grant date | May 30, 2006 |
| Priority date | — |
| Expiry date | Jun 14, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/46
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A successive approximation A/D converter includes first and second S/H and comparators sampling and holding first and second external analog input voltages simultaneously and comparing the held, first and second external analog input voltages with a reference voltage to output first and second signals having levels corresponding to resultant comparisons, and a reference voltage generator operative in response to the first and second signals to generate the reference voltage. The two S/H and comparators share the single reference voltage generator. A reduced chip area can be achieved.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.