On-die mechanism for high-reliability processor
US7055060B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 19, 2002 |
| Grant date | May 30, 2006 |
| Priority date | — |
| Expiry date | Nov 7, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2201/845
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor includes first and second execution cores that operate in a redundant (FRC) mode, an FRC check unit to compare results from the first and second execution cores, and an error check unit to detect recoverable errors in the first and second cores. The error detector disables the FRC checker, responsive to detection of a recoverable error. A multi-mode embodiment of the processor implements a multi-core mode in addition to the FRC mode. An arbitration unit regulates access to resources shared by the first and second execution cores in multi-core mode. The FRC checker is located proximate to the arbitration unit in the multi-mode embodiment.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.