Method of forming fin field effect transistor
US7056781B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 15, 2004 |
| Grant date | Jun 6, 2006 |
| Priority date | — |
| Expiry date | Dec 15, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/6213
Abstract
According to some embodiments, a fin type active region is formed under an exposure state of sidewalls on a semiconductor substrate. A gate insulation layer is formed on an upper part of the active region and on the sidewalls, and a device isolation film surrounds the active region to an upper height of the active region. The sidewalls are partially exposed by an opening part formed on the device isolation film. The opening part is filled with a conductive layer that partially covers the upper part of the active region, forming a gate electrode. Source and drain regions are on a portion of the active region where the gate electrode is not. The gate electrode may be easily separated and problems causable by etch by-product can be substantially reduced, and a leakage current of channel region and an electric field concentration onto an edge portion can be prevented.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.