FET gate structure with metal gate electrode and silicide contact
US7056794B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 9, 2004 |
| Grant date | Jun 6, 2006 |
| Priority date | — |
| Expiry date | May 1, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method is provided for fabricating a single-metal or dual metal replacement gate structure for a semiconductor device; the structure includes a silicide contact to the gate region. A dummy gate structure and sacrificial gate dielectric are removed to expose a portion of the substrate; a gate dielectric is formed thereon. A metal layer is formed overlying the gate dielectric and the dielectric material. This metal layer may conveniently be a blanket metal layer covering a device wafer. A silicon layer is then formed overlying the metal layer; this layer may also be a blanket wafer. A planarization or etchback process is then performed, so that the top surface of the dielectric material is exposed while other portions of the metal layer and the silicon layer remain in the gate region and have surfaces coplanar with the top surface of the dielectric material. A silicide contact is then formed which is in contact with the metal layer in the gate region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.