Bond pad
US7056820B2 · kind B2 · utility
12Cited by
8References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 20, 2003 |
| Grant date | Jun 6, 2006 |
| Priority date | — |
| Expiry date | Feb 6, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/14
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A bond pad upon which a wirebond interconnection is formed, consisting of a first bond pad layer formed on a chip, and a second bond pad layer formed on the first bond pad layer, wherein the first bond pad layer is more resistant to removal than the second bond pad layer during probe testing, and the first bond pad layer increases resistance to interconnection failure during mechanical testing.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.