Binary priority encoder
US7057546B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 18, 2004 |
| Grant date | Jun 6, 2006 |
| Priority date | — |
| Expiry date | Nov 19, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/74
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Apparatuses for binary priority encoding are described. A binary priority encoder (100, 100L) includes a data input bus (139), a first logic tree (110) coupled to receive data from the input bus (139), and a second logic tree (130) coupled to receive a portion of the data from the input bus (139). The first logic tree (110) is configured to provide a flag signal (154) indicating whether at least one bit of the data is active. The first logic tree (110) is configured to provide control signals. The second logic tree (130) is coupled to receive the control signals. The second logic tree (130) is configured to select first partial addresses from the portion of the data responsive to the control signals. The control signals are further provided to the second logic tree (130) as second partial addresses.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.