Semiconductor memory device with efficient multiplexing of I/O pad in multi-chip package
US7057964B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 20, 2004 |
| Grant date | Jun 6, 2006 |
| Priority date | — |
| Expiry date | Dec 20, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C5/066
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device includes: a memory core area; a plurality of address input pads for transferring addresses; a first address buffer part for receiving the addresses and outputting first addresses; a plurality of multi I/O pads for inputting/outputting data or inputting/outputting addresses/data while multiplexing the addresses/data; a data I/O buffer part for receiving data from the plurality of multi I/O pads and transferring the data to the memory core area or receiving and outputting addresses; a second address buffer part for receiving the addresses from the data I/O buffer part and outputting second addresses; an address multiplexer part for combining the first addresses and the second addresses and outputting data access addresses to the memory core area; and a path control part for controlling the address multiplexer part.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.