Method of generating an efficient stuck-at fault and transition delay fault truncated scan test pattern for an integrated circuit design
US7058909B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 3, 2003 |
| Grant date | Jun 6, 2006 |
| Priority date | — |
| Expiry date | Jun 14, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318328
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A method of generating a truncated scan test pattern for an integrated circuit design includes steps of: (a) receiving as input an integrated circuit design; (b) estimating a number of transition delay fault test patterns and a corresponding number of top-off stuck-at fault patterns to achieve maximum stuck-at fault and transition delay fault coverage; (c) truncating the estimated number of transition delay fault patterns to generate a truncated set of transition delay fault patterns so that the truncated set of transition delay fault patterns and the corresponding number of top-off stuck-at fault patterns achieve maximum stuck-at fault and transition delay fault coverage within a selected scan memory limit; and (d) generating as output the truncated set of transition delay fault patterns and the corresponding number of top-off stuck-at fault patterns.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.