Pin reordering during placement of circuit designs
US7058915B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 30, 2003 |
| Grant date | Jun 6, 2006 |
| Priority date | — |
| Expiry date | Jul 17, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/392
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method (400) of placing a circuit design can include the steps of identifying topological levels of a circuit design representation (415) and determining an arrival time for each input signal to a look up table within a circuit design representation (420). The propagation delay associated with each pin of the look up table can be identified (420) such that the input signals of the look up table can be ordered according to the arrival times of each input signal and the propagation delay of each pin of the look up table (435). The method can continue processing each look up table of an identified topological level (440) as well as each topological level of the circuit design representation (455).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.