Manufacturing method for a silicon substrate having strained layer
US7060597B2 · kind B2 · utility
3Cited by
7References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 18, 2004 |
| Grant date | Jun 13, 2006 |
| Priority date | — |
| Expiry date | Aug 19, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/02636
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A manufacturing method for a silicon substrate having a strained layer, has steps of forming a plurality of atomic steps having a height of 0.1 nm or more on the surface of a silicon substrate, forming a plurality of terraces having a width of 0.1 μm or more between the plurality of atomic steps and forming a SiGe layer or a SiGe layer and a Si layer on the silicon substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.