Methods of forming metal wiring of semiconductor devices including sintering the wiring layers and forming a via hole with a barrier metal
US7060603B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 19, 2003 |
| Grant date | Jun 13, 2006 |
| Priority date | — |
| Expiry date | Dec 19, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76864
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A formation method of metal wiring of a semiconductor device is disclosed. According to one example, an example method may include forming a metal wire on a pre metal dielectric (“PMD”) on a semiconductor substrate; patterning and sintering the metal wire; forming an insulating layer on the metal wire and the PMD; and forming a via hole in the insulating layer. The example method may further include forming a barrier metal layer made of multiple metal layers on inner wall of the via hole and upper surface of the insulating layer using physical vapor deposition and chemical vapor deposition; filling up inside the via hole by forming a metallic material on the metal layer; and forming a metallic material via by chemical mechanical polishing of the metallic material and the barrier metal layer until the insulating layer is exposed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.