Chip package structure and manufacturing method thereof
US7061079B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 17, 2004 |
| Grant date | Jun 13, 2006 |
| Priority date | — |
| Expiry date | Nov 17, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/1815
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention provides a chip package structure and the manufacturing method thereof, which affords higher heat dissipation efficiency and is suitable to fabricate the stack type package structure with a higher integration. The chip package structure comprises a carrier, at least a chip, a heat sink and a mold compound. The chip is disposed on the carrier, while the bonding pads of the chip are electrically connected to the leads of the carrier. The heat sink is disposed over the chip and includes at least a body and a plurality of connecting portions. The connecting portions are disposed around a periphery of the body and are electrically connected to the leads. By using a specially designed heat sink, the chip package structure can afford better heat dissipation and be suitable to form stack type package structures.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.