Arrangement of vias in a substrate to support a ball grid array
US7061116B2 · kind B2 · utility
3Cited by
7References
3Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 26, 2001 |
| Grant date | Jun 13, 2006 |
| Priority date | — |
| Expiry date | Jun 5, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2203/1394
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
An arrangement of pads with selective via in pad for mounting a semiconductor package on a substrate. In order to strengthen the soldered bonds, standard pads, which have a stronger bond, are used in locations of greatest stress and deflection. Vias in pad (VIP) are used at all other locations to improve routing advantages due to their smaller surface area.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.