Test circuit for delay lock loops
US7061224B2 · kind B2 · utility
5Cited by
6References
11Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 24, 2004 |
| Grant date | Jun 13, 2006 |
| Priority date | — |
| Expiry date | Sep 24, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0805
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method of testing a delay lock loop circuit is provided which comprises receiving an input signal and configuring the delay lock loop to generate a delay lock loop output signal based on the input signal. The method further comprises generating a test output signal from the input signal and delay lock loop output signal indicative of a relationship between a transition on the input signal and a transition on delay lock loop output signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.