Low AC power SRAM architecture
US7061792B1 · kind B1 · utility
1Cited by
35References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 10, 2002 |
| Grant date | Jun 13, 2006 |
| Priority date | — |
| Expiry date | Aug 10, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/002
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a SRAM structure, power consumption is reduced by providing a structure which allows specific memory cells to be selected using word lines and column select lines, and reducing the load on the column address lines by dividing the load into sectors. The dividing into sectors is achieved by making use of sector select lines for selecting two or more rows of cells, and logically ANDing the sector select lines with the column select lines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.