Voltage keeping scheme for low-leakage memory devices
US7061820B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 27, 2003 |
| Grant date | Jun 13, 2006 |
| Priority date | — |
| Expiry date | Aug 27, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/417
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention facilitates memory device operation by mitigating power consumption during suspend modes of operation, also referred to as sleep/data retention modes. This is accomplished by employing one or more gate-sinking voltage keeper components that operate as leakage current sinks during the suspend mode of operation instead of gate-sourcing voltage keeper components that operate as leakage current sources during the suspend mode of operation, on a circuit node whose voltage level is maintained by a sinking voltage regulator. As a result, less leakage current is required to be dissipated/sunk by a voltage regulator and/or other circuit paths or components of the memory device. Thus, relatively less power is consumed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.