Method and apparatus for reducing overhead in a data processing system with a cache
US7062610B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 30, 2002 |
| Grant date | Jun 13, 2006 |
| Priority date | — |
| Expiry date | Nov 11, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/126
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data processor (120) recognizes a special data processing operation in which data will be stored in a cache (124) for one use only. The data processor (120) allocates a memory location to at least one cache line of the cache (124). A data producer such as a data communication driver program running on a central processing unit (122) then writes a data element to the allocated memory location. A data consumer (160) reads the data element by sending a READ ONCE request to a host bridge (130). The host bridge (130) provides the READ ONCE request to a memory controller (126), which reads the data from the cache (124) and de-allocates the at least one cache line without performing a writeback from the cache to a main memory (170). In one form the memory controller (126) de-allocates the at least one cache line by issuing a probe marking the next state of the associated cache line as invalid.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.