Input/output cells for a double data rate (DDR) memory controller
US7062625B1 · kind B1 · utility
23Cited by
7References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 31, 2002 |
| Grant date | Jun 13, 2006 |
| Priority date | — |
| Expiry date | Nov 24, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1093
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An interface for sending write data, write control signals and write data between a memory controller and a double data rate (DDR) memory with the appropriate timing relationships so that the write data can be reliably written in the DDR memory. Also, an interface for reliably capturing read data received from the DDR memory during a read operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.