Processor and a method for handling and encoding no-operation instructions
US7062634B1 · kind B1 · utility
5Cited by
4References
26Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 29, 2002 |
| Grant date | Jun 13, 2006 |
| Priority date | — |
| Expiry date | Apr 13, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3853
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor is described in which the need to encode no-operation instructions (nops) in the program is minimised by providing a device for generating nops in response to information encoded in operative instructions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.