Test masks for lithographic and etch processes

US7062730B2 · kind B2 · utility

Assignee

• Praesagus, Inc. · US

Inventors

• David White · San Jose, US
• Taber H. Smith · San Jose, US

Key dates

• Filing date: Dec 17, 2002
• Grant date: Jun 13, 2006
• Expiry date: Apr 7, 2023

Classification

• Technology area (CPC —): General

Abstract

A mask design is generated for patterning a test wafer using a lithographic or etch process, the process is characterized based on the patterned test wafer, and a pattern-dependent model is used based on the characterization to predict characteristics of integrated circuits that are to be fabricated by the lithographic or etch process.