Technique for reducing contaminants in fabrication of semiconductor wafers
US7064073B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | May 9, 2003 |
| Grant date | Jun 20, 2006 |
| Priority date | — |
| Expiry date | Nov 10, 2023 |
Classification
- Technology area (CPC C)Chemistry; Metallurgy
- CPC primaryC23C16/4405
- WIPO fieldSurface technology, coating
- WIPO sectorChemistry
Abstract
According to one embodiment, a method for reducing contaminants in a reactor chamber is disclosed where the method comprises a step of etching the reactor chamber, which can comprise, for example, a dry etch process performed with hydrogen and HCL. Next, the reactor chamber is baked, which can comprise, for example, baking with hydrogen. Thereafter, an undoped semiconductor layer, such as an undoped silicon layer, is deposited in the reactor chamber to form a sacrificial semiconductor layer, for example, a sacrificial silicon layer. Then, the sacrificial semiconductor layer, for example, the sacrificial silicon layer, is removed from the reactor chamber. The removal step can comprise, for example, a dry etch process performed with HCL. In another embodiment, a wafer is fabricated in a reactor chamber that is substantially free of contaminants due to the implementation of the above method.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.