Advanced CMOS using super steep retrograde wells
US7064399B2 · kind B2 · utility
132Cited by
7References
5Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 7, 2001 |
| Grant date | Jun 20, 2006 |
| Priority date | — |
| Expiry date | Oct 20, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/60
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention is a method for forming super steep doping profiles in MOS transistor structures. The method comprises forming a carbon containing layer (110) beneath the gate dielectric (50) and source and drain regions (80) of a MOS transistor. The carbon containing layer (110) will prevent the diffusion of dopants into the region (40) directly beneath the gate dielectric layer (50).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.