Semiconductor multi-package module having wire bond interconnect between stacked packages
US7064426B2 · kind B2 · utility
80Cited by
40References
10Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Aug 2, 2003 |
| Grant date | Jun 20, 2006 |
| Priority date | — |
| Expiry date | Aug 2, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3025
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor multi-package module having stacked lower and upper packages, each package including a die attached to a substrate, in which the upper and lower substrates are interconnected by wire bonding. Also, a method for making a semiconductor multi-package module, by providing a lower molded package including a lower substrate and a die, affixing an upper molded package including an upper substrate onto the upper surface of the lower package, and forming z-interconnects between the upper and lower substrates.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.