Under bump metallization layer to enable use of high tin content solder bumps

US7064446B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• John Barnak · Beaverton, US
• Gerald Feldewerth · Spokane, US
• Ming Fang · Portland, US
• Kevin J. Lee · Beaverton, US
• Tzuen-Luh Huang · Portland, US
• Harry Liang · Portland, US
• Seshu V. Sattiraju · Portland, US
• Margherita Chang · Portland, US
• Andrew W. Yeoh · Portland, US

Key dates

• Filing date: Mar 29, 2004
• Grant date: Jun 20, 2006
• Expiry date: Jul 21, 2024

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2924/351
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Apparatus and methods of fabricating an under bump metallization structure including an adhesion layer abutting a conductive pad, a molybdenum-containing barrier layer abutting the adhesion layer, a wetting layer abutting the molybdenum-containing barrier layer, and high tin content solder material abutting the wetting layer. The wetting layer may be substantially subsumed in the high content solder forming an intermetallic compound layer. The molybdenum-containing barrier layer prevents the movement of tin in the high tin content solder material from migrating to dielectric layers abutting the conductive pad and potentially causing delamination and/or attacking any underlying structures, particularly copper structures, which may be present.