Method for locating IDDQ defects using multiple controlled collapse chip connections current measurement on an automatic tester
US7064570B2 · kind B2 · utility
4Cited by
7References
19Claims
0Family size
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Key dates
| Filing date | Sep 20, 2003 |
| Grant date | Jun 20, 2006 |
| Priority date | — |
| Expiry date | May 23, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/3012
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A method for improving the signal-to-noise ratio in an IDDQ defect test is disclosed. An integrated circuit is divided into a plurality of areas and each area is provided with and bounded by terminals. An IDDQ defect is activated to generate IDDQ defect current within the integrated circuit. An amount of IDDQ defect current generated within each area is measured at the terminals provided thereto. Based on the IDDQ current measurement on each area, an IDDQ current map is created. By analyzing the IDDQ current map, the presence and location of the defect is determined. Based on the determination, the IDDQ defect is isolated.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.