Distributed bus structure
US7064578B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 30, 2003 |
| Grant date | Jun 20, 2006 |
| Priority date | — |
| Expiry date | May 26, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/17736
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A programmable logic device includes a routing structure, which takes the form of multiple distributed OR gates, which are positioned within the device to allow signals to be input from spaced apart logic elements, and present the input signals to other logic elements, which, again, may be spaced apart throughout the device. Each of the distributed OR gates, and its connections to the other logic elements, acts as a multiplexer. Sufficient of these distributed OR gates are provided to allow a bus structure to be implemented within the device. Since the OR gates are provided separately from the logic elements of the programmable logic device, the required bus structure can be implemented more efficiently.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.