Method and apparatus for numeric optimization of the control of a delay-locked loop in a network device
US7064592B2 · kind B2 · utility
6Cited by
7References
15Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | May 14, 2004 |
| Grant date | Jun 20, 2006 |
| Priority date | — |
| Expiry date | Jul 2, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0816
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method of setting a delay offset in slave Delay-Locked Loop (DLL) modules by a master DLL module is disclosed. The method includes determining whether a delay tap value needs to be adjusted based on a comparison with a reference clock signal, calculating a delay offset value to correct the delay tap value, repeating the determining and calculating steps a predetermined number of times and forwarding a representative value of the calculated delay offset values. The representative value is determined through a comparison between all of the calculated delay offset values obtained in the repeating step.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.