Interface for prototyping integrated systems
US7065601B2 · kind B2 · utility
1Cited by
4References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 6, 2003 |
| Grant date | Jun 20, 2006 |
| Priority date | — |
| Expiry date | Jun 14, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2213/0038
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An interface is described which has at least one chip side port with a first plurality of pins for conveying fields of a packet and first and second circuit side ports each port having a set of pins with a lower number than the first set of pins in the chip side port. The interface is constructed so that interrupt signals from an off-chip circuit can be conveyed on-chip in a manner such that the interrupt signals are indistinguishable from interrupt signals received from on-chip modules connected to an on-chip communication path. The same principle is applicable to power-down signals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.