Interlocked synchronous pipeline clock gating
US7065665B2 · kind B2 · utility
20Cited by
7References
40Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 2, 2002 |
| Grant date | Jun 20, 2006 |
| Priority date | — |
| Expiry date | Jun 26, 2024 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit including a pipeline and a method of operating the pipeline. Each stage of the pipeline is triggered by one or more triggering events and are individually, and selectively, stalled by a stall signal. For each stage a stall signal, delayed with respect to the stall signal of a downstream stage, is generated and used to select whether the pipeline stage in question is triggered. A data valid signal propagating with valid data adds further selection, such that only stages with valid data are stalled.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.