Optimized bond out method for flip chip wafers
US7065721B2 · kind B2 · utility
5Cited by
16References
25Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 14, 2004 |
| Grant date | Jun 20, 2006 |
| Priority date | — |
| Expiry date | Dec 15, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/39
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of optimizing a bond out design includes steps of: (a) receiving as input an initial bond out design including at least one selected I/O pad and a top redistribution layer; (b) determining whether to include a lower redistribution layer in an optimized bond out design; (c) selecting a trace design to be included in the optimized bond out design for connecting the selected I/O pad to the top redistribution layer according to a bump function of the selected I/O pad; and (d) generating as output the optimized bond out design.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.