Vertical integrated package apparatus and method
US7067352B1 · kind B1 · utility
Inventor
Key dates
| Filing date | Mar 8, 2004 |
| Grant date | Jun 27, 2006 |
| Priority date | — |
| Expiry date | Jun 9, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/30105
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of fabricating integrated circuits from a plurality of semiconductor dice, each semiconductor die defining a top side and a bottom side, includes the steps of attaching the bottom sides of the plurality of semiconductor dice to a substrate so that the plurality of semiconductor dice are in adjacent disposition and define one or more bending regions; creating a thin film interconnect on the top sides of the plurality of semiconductor dice and over one or more die gap regions so that the plurality of semiconductor dice are electrically interconnected; removing the substrate from the bottom sides of the plurality of semiconductor dice; and bending the thin film interconnect at the one or more die gap regions so that the bottom sides and the top sides of the semiconductor dice overlap to form a stacked plurality of semiconductor dice.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.