Method of fabricating microelectronic package having a bumpless laminated interconnection layer
US7067356B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 28, 2003 |
| Grant date | Jun 27, 2006 |
| Priority date | — |
| Expiry date | Mar 14, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K3/4614
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A microelectronic device fabrication technology that places at least one microelectronic die within at least one opening in a microelectronic package core and secures the microelectronic die/dice within the opening(s) with an encapsulation material, that encapsulates at least one microelectronic die within an encapsulation material without a microelectronic package core, or that secures at least one microelectronic die within at least one opening in a heat spreader. A laminated interconnector of dielectric materials and conductive traces is then attached to the microelectronic die/dice and at least one of following: the encapsulation material, the microelectronic package core, and the heat spreader, to form a microelectronic device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.