Three-dimensional stacked semiconductor package with metal pillar in encapsulant aperture
US7067911B1 · kind B1 · utility
139Cited by
172References
150Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 15, 2004 |
| Grant date | Jun 27, 2006 |
| Priority date | — |
| Expiry date | Oct 15, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3512
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A three-dimensional stacked semiconductor package includes first and second semiconductor chip assemblies. The first semiconductor chip assembly includes a first chip, a first conductive trace and a first encapsulant, and the first conductive trace includes a first metal pillar. The second semiconductor chip assembly includes a second chip, a second conductive trace and a second encapsulant, and the second encapsulant includes a second aperture. The first metal pillar extends into the second aperture.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.