Dual chip stack method for electro-static discharge protection of integrated circuits
US7067914B2 · kind B2 · utility
12Cited by
6References
33Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 9, 2001 |
| Grant date | Jun 27, 2006 |
| Priority date | — |
| Expiry date | Nov 9, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/19104
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Disclosed is an electronic device comprising a semiconductor chip including an integrated circuit having at least one electrostatic discharge sensitive device and a non-semiconductor chip, positioned in close proximity to the semiconductor chip, the non-semiconductor chip having at least one electrostatic discharge protection device. The electrostatic discharge protection device is electrically connected to the electrostatic discharge sensitive device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.