Multi-level voltage output control circuit and logic gate therefor
US7068075B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 25, 2004 |
| Grant date | Jun 27, 2006 |
| Priority date | — |
| Expiry date | Jun 25, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/0013
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A multi-level voltage output control circuit selectively outputs one of multi-level power voltages by driving gates of two MOS transistors, which act as switching devices for the multi-level power voltages, with two output signals, the two output signals having complementary phases to each other and generated from two logic gates receiving two input signals which have an identical timing and complementary phases to each other, wherein the two logic gates advance or slow down a rising timing and/or a falling timing of the two output signals by differently adjusting a size of PMOS transistors and that of NMOS transistors, which construct the logic gates, thereby excluding a case in which the two output signals are in a same logic state at the same time.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.