CMOS image sensor with a low-power architecture
US7068319B2 · kind B2 · utility
19Cited by
19References
24Claims
0Family size
Assignee
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Key dates
| Filing date | Feb 1, 2002 |
| Grant date | Jun 27, 2006 |
| Priority date | — |
| Expiry date | May 8, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N25/78
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A system of reducing power consumption in and active pixels sensor. The sensor is broken into different blocks, and each of the blocks is individually optimized. The optimization may include minimizing the parasitic capacitance on the readout bus, turning off biases when not in use, and operating in a way that minimizes static power consumption of different elements such as A/D converters.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.