Semiconductor memory device
US7068551B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Feb 1, 2005 |
| Grant date | Jun 27, 2006 |
| Priority date | — |
| Expiry date | Feb 1, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Parasitic capacitances formed between bit lines to which signals are to be read out of memory cells and a signal transmission line arranged above them are to be reduced. Second complementary global bit lines for transmitting data read out of memory cells MC via complementary bit lines are arranged above a memory cell array. Each second global bit line is so arranged that a triangle having as its vertexes the center of the section of one of the complementary bit lines, that of the section of the other and that of the section of the second global bit line arranged directly above these complementary bit lines be an isosceles triangle.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.