Methods of fabricating fin field effect transistors having capping insulation layers
US7071048B2 · kind B2 · utility
28Cited by
2References
20Claims
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Key dates
| Filing date | Sep 8, 2004 |
| Grant date | Jul 4, 2006 |
| Priority date | — |
| Expiry date | Sep 8, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/00
Abstract
A field effect transistor includes a vertical fin-shaped semiconductor active region having an upper surface and a pair of opposing sidewalls on a substrate, and an insulated gate electrode on the upper surface and opposing sidewalls of the fin-shaped active region. The insulated gate electrode includes a capping gate insulation layer having a thickness sufficient to preclude formation of an inversion-layer channel along the upper surface of the fin-shaped active region when the transistor is disposed in a forward on-state mode of operation. Related fabrication methods are also discussed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.