Method for fabricating non-volatile memory
US7071061B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 26, 2005 |
| Grant date | Jul 4, 2006 |
| Priority date | — |
| Expiry date | Sep 26, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/037
Abstract
A method of fabricating a non-volatile memory is described. A substrate is provided and a first dielectric layer, an electron trapping layer and a second dielectric layer are sequentially formed thereon. Each of the stacked gate structures includes a first gate and a cap layer having a gap between every two stacked gate structures. An oxide layer is formed on the sidewalls of the first gate. A portion of the second dielectric layer not covered by the stacked gate structures is removed. A third dielectric layer is further formed on the substrate. A second conductive layer is formed over the substrate, and a portion thereof to form second gates. The second gates and the stacked gate structures form a column of memory cells. A source region and a drain region are formed in the substrate adjacent to two sides of the column of memory cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.