Layout optimization of integrated trench VDMOS arrays
US7071513B1 · kind B1 · utility
1Cited by
2References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 28, 2004 |
| Grant date | Jul 4, 2006 |
| Priority date | — |
| Expiry date | Oct 28, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/519
Abstract
An economical integration of trench VDMOS devices into a conventional BCD process is provided, with the optimization of key aspects of the device layout for low Rds(on) area. Specifically, trench orientation, array geometry, the number of source cells between drain pickups and drain-source spacing are independently optimized. In one embodiment of the invention, the optimized device utilizes a rectangular cell array with an elongation ratio in the range of 5/3–7/3, with a ratio of 5/3 being preferred, and a cell orientation at 45° with respect to the wafer flat on a 100 wafer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.