Stress mitigation layer to reduce under bump stress concentration
US7071554B2 · kind B2 · utility
9Cited by
4References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 27, 2004 |
| Grant date | Jul 4, 2006 |
| Priority date | — |
| Expiry date | Aug 24, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/30105
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In some embodiments, the invention provides a stress mitigation layer that reduces stress in a layer of a microelectronic device that is below a conductive connection structure, such as a bump.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.